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| DATASHEET TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER ICS345 Description The ICS345 field programmable clock synthesizer generates up to nine high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency crystal or clock input. It is designed to replace crystals and crystal oscillators in most electronic systems. Using IDT's VersaClockTM software to configure PLLs and outputs, the ICS345 contains a One-Time Programmable (OTP) ROM to allow field programmability. Programming features include eight selectable configuration registers, up to two sets of four low-skew outputs, and optional Spread Spectrum outputs. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The ICS345 is also available in factory programmed custom versions for high-volume applications. Features * * * * * * * * * * * * Packaged as 20-pin SSOP (QSOP) Spread spectrum capability Eight addressable registers Replaces multiple crystals and oscillators Output frequencies up to 200 MHz at 3.3 V Input crystal frequency of 5 to 27 MHz Input clock frequency of 2 to 50 MHz Up to nine reference outputs Up to two sets of four low-skew outputs Operating voltages of 3.3 V Advanced, low-power CMOS process For one output clock, use the ICS341. For two output clocks, see the ICS342. For three output clocks, see the ICS343. For more than three outputs, see the ICS345 or ICS348. Available in Pb (lead) free packaging * Block Diagram VDD 3 S 2:S 0 3 OTP ROM w ith P LL V alues P LL1 with S pread S pectrum D ivide Logic and O utput E nable C ontrol C LK 1 C LK 2 C LK 3 P LL2 C LK 4 C LK 5 C LK 6 C LK 7 C LK 8 C rystal or clock input X 1/IC LK C rystal O scillator X2 P LL3 C LK 9 E xternal capacitors are required w ith a crystal input. GND 2 PD TS IDTTM / ICSTM TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 1 ICS345 REV K 110207 ICS345 TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Pin Assignment X1/ICLK S0 S1 CLK9 VDD GND CLK1 CLK2 CLK3 CLK4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 X2 VDD PDTS S2 VDD GND CLK5 CLK6 CLK7 CLK8 20-pin (150 mil) SSOP (QSOP) Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name X1/ICLK S0 S1 CLK9 VDD GND CLK1 CLK2 CLK3 CLK4 CLK8 CLK7 CLK6 CLK5 GND VDD S2 PDTS VDD X2 Pin Type XI Input Input Output Power Power Output Output Output Output Output Output Output Output Power Power Input Input Power XO Pin Description Crystal input. Connect this pin to a crystal or external input clock. Select pin 0. Internal pull-up resistor. Select pin 1. Internal pull-up resistor. Output clock 9. Weak internal pull-down when tri-state. Connect to +3.3 V. Connect to ground. Output clock 1. Weak internal pull-down when tri-state. Output clock 2. Weak internal pull-down when tri-state. Output clock 3. Weak internal pull-down when tri-state. Output clock 4. Weak internal pull-down when tri-state. Output clock 8. Weak internal pull-down when tri-state. Output clock 7. Weak internal pull-down when tri-state. Output clock 6. Weak internal pull-down when tri-state. Output clock 5. Weak internal pull-down when tri-state. Connect to ground. Connect to +3.3 V. Select pin 2. Internal pull-up resisitor. Power-down tri-state. Powers down entire chip and tri-states clock outputs when low. Internal pull-up resisitor. Connect to +3.3 V. Crystal Output. Connect this pin to a crystal. Float for clock input. IDTTM / ICSTM TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 2 ICS345 REV K 110207 ICS345 TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER External Components Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 . they should be separated and away from other traces. 3) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS345 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. ICS345 Configuration Capabilities The architecture of the ICS345 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The ICS345 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as: OutputFreq Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2 = 20]. = REFFreq ------------------------------------OutputDivide M ---N IDT VersaClock Software IDT applies years of PLL optimization experience into a user friendly software that accepts the user's target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead IDTTM / ICSTM TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 3 ICS345 REV K 110207 ICS345 TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Spread Spectrum Modulation The ICS345 utilizes frequency modulation (FM) to distribute energy over a range of frequencies. By modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system's electromagnetic interference (EMI). The modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. Spread Spectrum Modulation can be applied as either "center spread" or "down spread". During center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. The effective average frequency is equal to the target frequency. In applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. In this case, the maximum frequency, including modulation, is the target frequency. The effective average frequency is less than the target frequency. The ICS345 operates in both center spread and down spread modes. For center spread, the frequency can be modulated between 0.125% to 2.0%. For down spread, the frequency can be modulated between -0.25% to -4.0%. Both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common VCO frequency can be identified. Spread Spectrum Modulation Rate The spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. For applications requiring the driving of "down-circuit" PLLs, Zero Delay Buffers, or those adhering to PCI standards, the spread spectrum modulation rate should be set to 30-33 kHz. For other applications, a 120 kHz modulation option is available. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS345. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Supply Voltage, VDD Inputs Clock Outputs Storage Temperature Soldering Temperature Junction Temperature Condition Referenced to GND Referenced to GND Referenced to GND Max 10 seconds Min. -0.5 -0.5 -65 Typ. Max. 7 VDD+0.5 VDD+0.5 150 260 125 Units V V V C C C IDTTM / ICSTM TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 4 ICS345 REV K 110207 ICS345 TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Recommended Operation Conditions Parameter Ambient Operating Temperature (ICS345RP) Ambient Operating Temperature (ICS345RIP) Power Supply Voltage (measured in respect to GND) Power Supply Ramp Time Min. 0 -40 +3.15 Typ. Max. +70 +85 Units C C V ms +3.3 +3.45 4 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C Parameter Operating Voltage Operating Supply Current Input High Voltage Symbol VDD IDD Conditions Configuration Dependent See VersaClockTM Estimates Nine 33.3333 MHz outs, PDTS = 1, no load, Note 1 Min. 3.15 Typ. Max. 3.45 Units V mA 23 20 2 0.4 VDD-0.5 0.4 mA A V V V V V VDD/2-1 V V V 0.4 V mA k k pF Input High Voltage Input Low Voltage Input High Voltage, PDTS Input Low Voltage, PDTS Input High Voltage Input Low Voltage Output High Voltage (CMOS High) Output High Voltage Output Low Voltage Short Circuit Current Nominal Output Impedance Internal Pull-up Resistor Internal Pull-down Resistor Input Capacitance VIH VIL VIH VIL VIH VIL VOH VOH VOL IOS ZO RPUS RPD CIN PDTS = 0, no load, Note 1 S2:S0 S2:S0 ICLK ICLK IOH = -4 mA IOH = -12 mA IOL = 12 mA VDD/2+1 VDD-0.4 2.4 70 20 S2:S0, PDTS CLK outputs Inputs 250 525 4 Note 1: Example with 25 MHz crystal input with nine outputs of 33.3 MHz, no load, and VDD = 3.3 V. IDTTM / ICSTM TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 5 ICS345 REV K 110207 ICS345 TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C Parameter Input Frequency Output Frequency Output Rise Time Output Fall Time Duty Cycle Output Frequency Synthesis Error (Note 4) Power-up Time Symbol FIN Conditions Fundamental crystal Input clock VDD=3.3 V Min. 5 2 0.25 Typ. Max. Units 27 50 200 MHz MHz MHz ns ns 60 % ppm 10 2 ms ms tOR tOF 20% to 80%, Note 1 80% to 20%, Note 1 Note 2 Configuration Dependent PLL lock-time from power-up, Note 3 PDTS goes high until stable CLK output, Spread Spectrum Off, Note 3 PDTS goes high until stable CLK output, Spread Spectrum On, Note 3 40 1 1 49-51 0 4 0.2 4 7 ms One Sigma Clock Period Jitter Maximum Absolute Jitter Pin-to-Pin Skew Note 1: Measured with 15 pF load. tja Configuration Dependent Deviation from Mean. Configuration Dependent Low Skew Outputs -250 50 +200 250 ps ps ps Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55% Note 3: IDT test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS transition high on select address change. Note 4: The actual ppm error will be displayed in the VersaClock software when the programming file is generated for the customer's specific configuration. In general, zero ppm error can be achieved, but please note that the device cannot improve upon the error of the input reference clock. For example, if the input crystal has 25 ppm error, then the outputs will also have 25 ppm error. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 135 93 78 60 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case IDTTM / ICSTM TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 6 ICS345 REV K 110207 ICS345 TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 20 Inches* Min Max Symbol Min Max E1 INDEX AREA E 12 D A A1 A2 b c D E E1 e L aaa 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 .635 Basic 0.40 1.27 0 8 -0.10 0.053 0.069 0.004 0.010 -0.059 0.008 0.012 0.007 0.010 0.337 0.344 0.228 0.244 0.150 0.157 .025 Basic 0.016 0.050 0 8 -0.004 A2 A1 A *For reference only. Controlling dimensions in mm. c -Ce b SEATING PLANE L aaa C IDTTM / ICSTM TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 7 ICS345 REV K 110207 ICS345 TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Ordering Information Part / Order Number ICS345RP ICS345RPT ICS345RIP ICS345RIPT ICS345RPLF ICS345RPLFT ICS345RIPLF ICS345RIPLFT ICS345R-XX ICS345R-XXT ICS345RI-XX ICS345RI-XXT ICS345R-XXLF ICS345R-XXLFT ICS345RI-XXLF ICS345RI-XXLFT Marking ICS345RP ICS345RP ICS345RIP ICS345RIP ICS345RPLF ICS345RPLF ICS345RIPLF ICS345RIPLF ICS345R-XX ICS345R-XX ICS345RI-XX ICS345RI-XX 345R-XXLF 345R-XXLF 345RI-XXLF 345RI-XXLF Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP Temperature 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The ICS345R-XX, ICS345R-XXLF, ICS345RI-XX, and ICS345RI-XXLF are factory programmed versions of the ICS345RP, ICS345RPLF, ICS345RIP, and ICS345RIPLF. A unique "-XX" suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 8 ICS345 REV K 110207 ICS345 TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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